In general, a liquid crystal display (LCD) includes an LCD panel, a gate driver, and a source driver. The LCD panel may include a lower glass substrate (TFT array) on which thin transistors and pixel electrodes are arranged; an upper glass substrate that includes a color filter for color representation, and common electrodes; and a liquid crystal between the lower and upper glass substrates. Also, a polarizing plate that linearly polarizes visible light may be attached to the both side surfaces of the upper and lower glass substrates.
In the TFT array, a plurality of source lines and a plurality of gate lines are arranged to connect pixels in the form of a matrix. Each pixel may have a thin film transistor (TFT) and a capacitor.
The gate driver sequentially drives the gate lines of the TFT-LCD panel. The source driver transforms digital data (source data), which may be a video signal, into analog voltages to drive the source lines of the LCD panel.
FIG. 1 is a block diagram of a general LCD driver integrated circuit (LDI) 100. Referring to FIG. 1, the LDI 100 includes a reduced swing differential signaling (RSDS) receiver 110, a data register unit 120, a shift register unit 130, a data latch unit 140, a decoder 150, and an output buffer 160.
The RSDS receiver 110 receives a plurality of digital signals D00P, D00N, D01P, D01N, . . . , D22P, and D22N from a central processing unit (CPU) (not shown). The digital signals D00P, D00N, D01P, D01N, . . . , D22P, and D22N may be transmitted according to an RSDS method. The data register unit 120 receives and stores in parallel 3×N bit digital data from the RSDS receiver 110 (N denotes the number of bits for each channel). Here, N is set to 6. That is, it is assumed that each channel data is 6 bits long.
Data stored in the data register unit 120 are transmitted to the data latch unit 140 in response to latch clock signals received from the shift register unit 130. When channel data regarding all channels (n channels) is stored in the data latch unit 140, the data latch unit 140 transmits n×N bit data to the decoder 150 in response to a first clock signal CLK1 (n denotes the number of channels).
The decoder 150 receives n channel data from the data latch unit 140 at a time, and outputs gamma voltages corresponding to the n channel data, respectively. The output buffer 160 buffers the gamma voltages from the decoder 150 to generate driving voltages Y1, Y2, Y3, . . . , Yn-2, Yn-1, and Yn, and outputs the driving voltages Y1, Y2, Y3, . . . , Yn-2, Y n-1, and Yn to corresponding source lines (channels).
The LDI 100 further includes a logic controller (not shown). The logic controller controls the operation of the LDI 100 in response to control signals output from the CPU.
FIG. 2 is a block diagram of a conventional LDI 200. Referring to FIG. 2, like general LDIs, the conventional LDI 200 includes shift register units 210a and 210b, data latch units 220a and 220b, decoders 230a and 230b, output buffers 240a and 240b, and a logic controller 250. The conventional LDI 200 further includes an input signal pad unit 260 via which external signals are received. Other components also may be included.
In a conventional LDI 200, the shift register units 210a and 210b, the data latch units 220a and 220b, the decoders 230a and 230b, and the output buffers 240a and 240b are located in a line to the right and left sides of the logic controller 250, respectively. That is, the logic controller 250 is located at the center of the Integrated Circuit (IC) chip; a first group of the shift register unit 210a the data latch unit 220a, the decoder 230a, and the output buffer 240a are arranged in a line to the left side of the logic controller 250; and a second group of the shift register unit 210a, the data latch unit 220a, the decoder 230a, and the output buffer 240a are arranged in a line to the right side of the logic controller 250.
Conventional LDIs generally have the above in-line structure in which output buffers are arranged in a line along a long edge of the chip, and therefore, the more channels, the longer the long edge of the LDI. Accordingly, in the conventional LDIs, a long edge may be ten times longer than a short edge, and the more channels, the poorer the output characteristics between channels may be and/or the more difficult the chip fabrication may be. The length of a long edge of the LDI may also cause serious restrictions to a large-scale panel, e.g., a display system, which needs more than one LDI.